As author R. Jacob “Jake” Baker points out in the preface to this comprehensive volume, CMOS technology has dominated the fabrication of ICs for 25 years, and is likely to dominate it for another 25 ...

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...

In our first two chapters, we constructed individual devices. We built the various layers of each device from the ground up, creating a transistor, for example. Integrated circuits, as you know, are ...

November 11, 2022 -- Semiwise has developed transistor SPICE models based on the GlobalFoundries (GF) 22FDX ® Platform that enable cryogenic CMOS design and verification. Using its patented ...

In recent years we have begun to see references to “RF” CMOS processes and to “RF” models for those processes. This article will explore what the real meanings of such “RF” designations are, and what ...

Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying ...

Technologists describe a straight port of an existing bulk CMOS design to FD-SOI at the same node, obtaining the value of fully depleted SOI for a modest redesign effort. November 16th, 2012 - By: ...

MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process ...

Finishing up on the topic of CMOS bus logic I am going to show a couple of families with unique properties that may come in handy one day. First up is a CMOS logic family AHC/AHCT that has one of the ...